1. Field of the Invention
This invention relates to mesa isolation and, more specifically, to a method of mesa isolation and the isolated mesa structure.
2. Brief Description of the Prior Art
The procedure generally used for mesa isolation in silicon-on-insulator (SOI) technology is to provide an oxide (insulator) layer which becomes a buried layer after a layer of silicon is formed thereon and then etching the silicon to form silicon mesas on the buried layer with portions of the buried layer being exposed. A major problem with the above-described mesa isolation scheme utilized in current silicon on insulator (SOI) processes is that the exposed buried oxide insulator is reduced in thickness during processing. This reduction in the buried oxide insulator thickness leads to possible exposure of type II buried oxide defects, such defects causing short circuits between the substrate beneath the buried oxide and an electrical conductor such as polycrystalline silicon (polysilicon) on the reduced thickness buried oxide. The thinning of the buried oxide also leads to high interconnect capacitance, thereby reducing one of the major advantages of SOI technology. It is therefore apparent that a process which will minimize such buried oxide thinning and/or compensate for such buried oxide thinning is highly desirable.